//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef __BULVERDE_H
#define __BULVERDE_H

/*
 * Bulverde Definitions
 */

#if defined(__HAVENOT_USEMMU)
#define __REG(x)    (*(volatile unsigned long*)(x))
#else
#define __REG(x)    (*(volatile unsigned long*)((x)+(unsigned long)0x40000000/*1G*/))
#endif

#define MEMC_BASE       0x48000000
#define SDRAM0_BASE     0xA0000000
#define SDRAM1_BASE     0xA8000000
#define OSCR_BASE       0x40A00010
#define FPGA_REGS_BASE  0x08000000

// /////////////////////////////////////////////////////////////////////////////////////////
// /* RELEVANT REGISTER-SPECIFIC OFFSETS */
// /////////////////////////////////////////////////////////////////////////////////////////

////
//// MEMC
////
#define MDCNFG_OFFSET                        0x0
#define MDREFR_OFFSET                        0x4
#define MSC0_OFFSET                          0x8
#define MSC1_OFFSET                          0xC
#define MSC2_OFFSET                          0x10
#define MECR_OFFSET                          0x14
#define SXCNFG_OFFSET                        0x1C
#define FLYCNFG_OFFSET                       0x20
#define MCMEM0_OFFSET                        0x28
#define MCMEM1_OFFSET                        0x2C
#define MCATT0_OFFSET                        0x30
#define MCATT1_OFFSET                        0x34
#define MCIO0_OFFSET                         0x38
#define MCIO1_OFFSET                         0x3C
#define MDMRS_OFFSET                         0x40
#define BOOT_DEF_OFFSET                      0x44
#define ARB_CNTL_OFFSET                      0x48
#define BSCNTR0_OFFSET                       0x4C
#define BSCNTR1_OFFSET                       0x50
#define LCDBSCNTR_OFFSET                     0x54
#define MDMRSLP_OFFSET                       0x58
#define BSCNTR2_OFFSET                       0x5C
#define BSCNTR3_OFFSET                       0x60

////
//// FULL-FEATURE UART
////
#define FFTHR_OFFSET                        0x0      //DLAB = 0  WO  8bit - Transmit Holding Register
#define FFRBR_OFFSET                        0x0      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define FFDLL_OFFSET                        0x0      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define FFIER_OFFSET                        0x4      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define FFDLH_OFFSET                        0x4      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define FFIIR_OFFSET                        0x8      //DLAB = X  RO  8bit - Interrupt Identification Register
#define FFFCR_OFFSET                        0x8      //DLAB = X  WO  8bit - FIFO Control Register
#define FFLCR_OFFSET                        0xC      //DLAB = X  RW  8bit - Line Control Register
#define FFMCR_OFFSET                        0x10      //DLAB = X  RW  8bit - Modem Control Regiser
#define FFLSR_OFFSET                        0x14      //DLAB = X  RO  8bit - Line Status Register
#define FFMSR_OFFSET                        0x18      //DLAB = X  RO  8bit - Modem Status Register
#define FFSPR_OFFSET                        0x1C      //DLAB = X  RW  8bit - Scratchpad Register
#define FFISR_OFFSET                        0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
#define FFFOR_OFFSET                        0x24      //DLAB = X  RO  FIFO Occupancy Register
#define FFABR_OFFSET                        0x28      //DLAB = X  RW  Autobaud Control Register
#define FFACR_OFFSET                        0x2C      //DLAB = X Autobaud Count Register

////
//// BLUETOOTH UART
////
#define BTTHR_OFFSET                        0x0      //DLAB = 0  WO  8bit - Transmit Holding Register
#define BTRBR_OFFSET                        0x0      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define BTDLL_OFFSET                        0x0      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define BTIER_OFFSET                        0x4      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define BTDLH_OFFSET                        0x4      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define BTIIR_OFFSET                        0x8      //DLAB = X  RO  8bit - Interrupt Identification Register
#define BTDLL_OFFSET                        0x0      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define BTIER_OFFSET                        0x4      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define BTDLH_OFFSET                        0x4      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define BTIIR_OFFSET                        0x8      //DLAB = X  RO  8bit - Interrupt Identification Register
#define BTFCR_OFFSET                        0x8      //DLAB = X  WO  8bit - FIFO Control Register
#define BTLCR_OFFSET                        0xC      //DLAB = X  RW  8bit - Line Control Register
#define BTMCR_OFFSET                        0x10      //DLAB = X  RW  8bit - Modem Control Regiser
#define BTLSR_OFFSET                        0x14      //DLAB = X  RO  8bit - Line Status Register
#define BTMSR_OFFSET                        0x18      //DLAB = X  RO  8bit - Modem Status Register
#define BTSPR_OFFSET                        0x1C      //DLAB = X  RW  8bit - Scratchpad Register
#define BTISR_OFFSET                        0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
#define BTFOR_OFFSET                        0x24      //DLAB = X  RO  FIFO Occupancy Register
#define BTABR_OFFSET                        0x28      //DLAB = X  RW  Autobaud Control Register
#define BTACR_OFFSET                        0x2C      //DLAB = X Autobaud Count Register

////
//// STANDARD UART
////
#define STTHR_OFFSET                        0x0      //DLAB = 0  WO  8bit - Transmit Holding Register
#define STRBR_OFFSET                        0x0      //DLAB = 0  RO  8bit - Recieve Buffer Register
#define STDLL_OFFSET                        0x0      //DLAB = 1  RW  8bit - Divisor Latch Low Register
#define STIER_OFFSET                        0x4      //DLAB = 0  RW  8bit - Interrupt Enable Register
#define STDLH_OFFSET                        0x4      //DLAB = 1  RW  8bit - Divisor Latch High Register
#define STIIR_OFFSET                        0x8      //DLAB = X  RO  8bit - Interrupt Identification Register
#define STFCR_OFFSET                        0x8      //DLAB = X  WO  8bit - FIFO Control Register
#define STLCR_OFFSET                        0xC      //DLAB = X  RW  8bit - Line Control Register
#define STMCR_OFFSET                        0x10      //DLAB = X  RW  8bit - Modem Control Regiser
#define STLSR_OFFSET                        0x14      //DLAB = X  RO  8bit - Line Status Register
#define STMSR_OFFSET                        0x18      //DLAB = X  RO  8bit - Modem Status Register
#define STSPR_OFFSET                        0x1C      //DLAB = X  RW  8bit - Scratchpad Register
#define STISR_OFFSET                        0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
#define STFOR_OFFSET                        0x24      //DLAB = X  RO  FIFO Occupancy Register
#define STABR_OFFSET                        0x28      //DLAB = X  RW  Autobaud Control Register
#define STACR_OFFSET                        0x2C      //DLAB = X Autobaud Count Register

////
//// RTC
////
#define RCNR_OFFSET                          0x0      //RTC count register
#define RTAR_OFFSET                          0x4      //RTC alarm register
#define RTSR_OFFSET                          0x8      //RTC status register
#define RTTR_OFFSET                          0xC      //RTC timer trim register
#define RDCR_OFFSET                          0x10     //RTC Day Counter
#define RYCR_OFFSET                          0x14     //RTC Year Counter
#define RDAR1_OFFSET                         0x18     //RTC Day Alarm 1
#define RYAR1_OFFSET                         0x1C     //RTC Year Alarm 1
#define RDAR2_OFFSET                         0x20     //RTC Day Alarm 2
#define RYAR2_OFFSET                         0x24     //RTC Year Alarm 2
#define SWCR_OFFSET                          0x28     //RTC Stopwatch Counter
#define SWAR1_OFFSET                         0x2C     //RTC Stopwatch Alarm 1
#define SWAR2_OFFSET                         0x30     //RTC Stopwatch Alarm 2
#define PICR_OFFSET                          0x34     //RTC Periodic Interrupt Counter
#define PIAR_OFFSET                          0x38     //RTC Periodic Interrupt Alarm

////
//// OST (OS TIMER)
////
#define OSMR0_OFFSET                         0x0      //OS timer match register 0
#define OSMR1_OFFSET                         0x4      //OS timer match register 1
#define OSMR2_OFFSET                         0x8      //OS timer match register 2
#define OSMR3_OFFSET                         0xC      //OS timer match register 3
#define OSCR0_OFFSET                         0x10      //OS timer counter register 0
#define OSSR_OFFSET                          0x14      //OS timer status register
#define OWER_OFFSET                          0x18      //OS timer watchdog enable register
#define OIER_OFFSET                          0x1C      //OS timer interrupt enable register
#define OSCR4_OFFSET                         0x40
#define OSCR5_OFFSET                         0x44
#define OSCR6_OFFSET                         0x48
#define OSCR7_OFFSET                         0x4C
#define OSCR8_OFFSET                         0x50
#define OSCR9_OFFSET                         0x54
#define OSCR10_OFFSET                        0x58
#define OSCR11_OFFSET                        0x5C
#define OSMR4_OFFSET                         0x80
#define OSMR5_OFFSET                         0x84
#define OSMR6_OFFSET                         0x88
#define OSMR7_OFFSET                         0x8C
#define OSMR8_OFFSET                         0x90
#define OSMR9_OFFSET                         0x94
#define OSMR10_OFFSET                        0x98
#define OSMR11_OFFSET                        0x9C
#define OMCR4_OFFSET                         0xC0
#define OMCR5_OFFSET                         0xC4
#define OMCR6_OFFSET                         0xC8
#define OMCR7_OFFSET                         0xCC
#define OMCR8_OFFSET                         0xD0
#define OMCR9_OFFSET                         0xD4
#define OMCR10_OFFSET                        0xD8
#define OMCR11_OFFSET                        0xDC

////
//// INTC (INTERRUPT CONTROLLER) - Memory-mapped addresses (can also use c-proc for most of these)
////
#define ICIP_OFFSET                          0x0      //Interrupt controller IRQ pending register
#define ICMR_OFFSET                          0x4      //Interrupt controller mask register
#define ICLR_OFFSET                          0x8      //Interrupt controller level register
#define ICFP_OFFSET                          0xC      //Interrupt controller FIQ pending register
#define ICPR_OFFSET                          0x10     //Interrupt controller pending register
#define ICCR_OFFSET                          0x14     //Interrupt controller control register
#define ICHP_OFFSET                          0x18     //Interrupt controller Highest Priority register
#define IPR0_OFFSET                          0x1C     //Interrupt controller Priority registerS [31:0]
#define IPR1_OFFSET                          0x20
#define IPR2_OFFSET                          0x24
#define IPR3_OFFSET                          0x28
#define IPR4_OFFSET                          0x2C
#define IPR5_OFFSET                          0x30
#define IPR6_OFFSET                          0x34
#define IPR7_OFFSET                          0x38
#define IPR8_OFFSET                          0x3C
#define IPR9_OFFSET                          0x40
#define IPR10_OFFSET                          0x44
#define IPR11_OFFSET                          0x48
#define IPR12_OFFSET                          0x4C
#define IPR13_OFFSET                          0x50
#define IPR14_OFFSET                          0x54
#define IPR15_OFFSET                          0x58
#define IPR16_OFFSET                          0x5C
#define IPR17_OFFSET                          0x60
#define IPR18_OFFSET                          0x64
#define IPR19_OFFSET                          0x68
#define IPR20_OFFSET                          0x6C
#define IPR21_OFFSET                          0x70
#define IPR22_OFFSET                          0x74
#define IPR23_OFFSET                          0x78
#define IPR24_OFFSET                          0x7C
#define IPR25_OFFSET                          0x80
#define IPR26_OFFSET                          0x84
#define IPR27_OFFSET                          0x88
#define IPR28_OFFSET                          0x8C
#define IPR29_OFFSET                          0x90
#define IPR30_OFFSET                          0x94
#define IPR31_OFFSET                          0x98

////
//// GPIO
////
#define GPLR0_OFFSET                        0x0      //GPIO pin-level register 31:0
#define GPLR1_OFFSET                        0x4      //GPIO pin-level register 63:32
#define GPLR2_OFFSET                        0x8      //GPIO pin-level register 95:64
#define GPDR0_OFFSET                        0xC      //GPIO pin-direction register 31:0
#define GPDR1_OFFSET                        0x10      //GPIO pin-direction register 63:32
#define GPDR2_OFFSET                        0x14      //GPIO pin-direction register 95:64
#define GPSR0_OFFSET                        0x18      //GPIO pin output set register 31:0
#define GPSR1_OFFSET                        0x1C      //GPIO pin output set register 63:32
#define GPSR2_OFFSET                        0x20      //GPIO pin output set register 95:64
#define GPCR0_OFFSET                        0x24      //GPIO pin output clear register 31:0
#define GPCR1_OFFSET                        0x28      //GPIO pin output clear register 63:32
#define GPCR2_OFFSET                        0x2C      //GPIO pin output clear register 95:64
#define GRER0_OFFSET                        0x30      //GPIO rising edge detect register 31:0
#define GRER1_OFFSET                        0x34      //GPIO rising edge detect register 63:32
#define GRER2_OFFSET                        0x38      //GPIO rising edge detect register 95:64
#define GFER0_OFFSET                        0x3C      //GPIO falling edge detect register 31:0
#define GFER1_OFFSET                        0x40      //GPIO falling edge detect register 63:32
#define GFER2_OFFSET                        0x44      //GPIO falling edge detect register 95:64
#define GEDR0_OFFSET                        0x48      //GPIO edge detect status register 31:0
#define GEDR1_OFFSET                        0x4C      //GPIO edge detect status register 63:32
#define GEDR2_OFFSET                        0x50      //GPIO edge detect status register 95:64
#define GAFR0_L_OFFSET                       0x54      //GPIO alternate funciton select register 15:0
#define GAFR0_U_OFFSET                       0x58      //GPIO alternate function select register 31:16
#define GAFR1_L_OFFSET                       0x5C      //GPIO alternate function select register 47:32
#define GAFR1_U_OFFSET                       0x60      //GPIO alternate function select register 63:48
#define GAFR2_L_OFFSET                       0x64      //GPIO alternate function select register 79:64
#define GAFR2_U_OFFSET                       0x68      //GPIO alternate function select register 95:80
#define GAFR3_L_OFFSET                       0x6C      //GPIO alternate function select register 111:96
#define GAFR3_U_OFFSET                       0x70      //GPIO alternate function select register 120:112
#define GPLR3_OFFSET                         0x100     //GPIO pin-level register 120:96
#define GPDR3_OFFSET                         0x10C     //GPIO pin-direction register 120:96
#define GPSR3_OFFSET                         0x118     //GPIO pin output set register 120:96
#define GPCR3_OFFSET                         0x124     //GPIO pin output clear register 120:96
#define GRER3_OFFSET                         0x130     //GPIO rising edge detect register 120:96
#define GFER3_OFFSET                         0x13C     //GPIO falling edge detect register 120:96
#define GEDR3_OFFSET                         0x148     //GPIO edge detect status register 120:96

////
//// POWER MANAGER & RESET CONTROLLER
////
#define PMCR_OFFSET                          0x0      //Power manager control register
#define PSSR_OFFSET                          0x4      //Power manager sleep status register
#define PSPR_OFFSET                          0x8      //Power manager scratch pad register
#define PWER_OFFSET                          0xC      //Power manager wake-up enable register
#define PRER_OFFSET                          0x10      //Power manager GPIO rising edge detect enable register
#define PFER_OFFSET                          0x14      //Power manager GPIO falling edge detect enable register
#define PEDR_OFFSET                          0x18      //Power manager GPIO edge detect status register
#define PCFR_OFFSET                          0x1C      //Power manager general configuration register
#define PGSR0_OFFSET                         0x20      //Power manager GPIO sleep state register for GPIO 31:0
#define PGSR1_OFFSET                         0x24      //Power manager GPIO sleep state register for GPIO 63:32
#define PGSR2_OFFSET                         0x28      //Power manager GPIO sleep state register for GPIO 95:64
#define PGSR3_OFFSET                         0x2C      //Power manager GPIO sleep state register for GPIO 120:96
#define RCSR_OFFSET                          0x30      // **Reset controller status register**
#define PSLR_OFFSET                          0x34      //Power manager Sleep Mode Config
#define PSTR_OFFSET                          0x38      //Power manager Standby Mode Config
#define PSNR_OFFSET                          0x3C      //Power manager Sense Mode Config
#define PVCR_OFFSET                          0x40      //Power manager Voltage Change Control
#define PCMD0_OFFSET                         0x80      //Power manager I2C Command[31:0]
#define PCMD1_OFFSET                         0x84
#define PCMD2_OFFSET                         0x88
#define PCMD3_OFFSET                         0x8C
#define PCMD4_OFFSET                         0x90
#define PCMD5_OFFSET                         0x94
#define PCMD6_OFFSET                         0x98
#define PCMD7_OFFSET                         0x9C
#define PCMD8_OFFSET                         0xA0
#define PCMD9_OFFSET                         0xA4
#define PCMD10_OFFSET                        0xA8
#define PCMD11_OFFSET                        0xAC
#define PCMD12_OFFSET                        0xB0
#define PCMD13_OFFSET                        0xB4
#define PCMD14_OFFSET                        0xB8
#define PCMD15_OFFSET                        0xBC
#define PCMD16_OFFSET                        0xC0
#define PCMD17_OFFSET                        0xC4
#define PCMD18_OFFSET                        0xC8
#define PCMD19_OFFSET                        0xCC
#define PCMD20_OFFSET                        0xD0
#define PCMD21_OFFSET                        0xD4
#define PCMD22_OFFSET                        0xD8
#define PCMD23_OFFSET                        0xDC
#define PCMD24_OFFSET                        0xE0
#define PCMD25_OFFSET                        0xE4
#define PCMD26_OFFSET                        0xE8
#define PCMD27_OFFSET                        0xEC
#define PCMD28_OFFSET                        0xF0
#define PCMD29_OFFSET                        0xF4
#define PCMD30_OFFSET                        0xF8
#define PCMD31_OFFSET                        0xFC
#define PIBMR_OFFSET                         0x180     //Power manager I2C Bus Monitor
#define PIDBR_OFFSET                         0x188     //Power manager I2C Data Buffer
#define PI2CR_OFFSET                         0x190     //Power manager I2C Control
#define PISR_OFFSET                          0x198     //Power manager I2C Status
#define PISAR_OFFSET                         0x1A0     //Power manager I2C Slave Address

////
//// CLK MAN
////
#define CCCR_OFFSET                          0x0      //Core Clock Configuration Register
#define CKEN_OFFSET                          0x4      //Clock Enable Register
#define OSCC_OFFSET                          0x8      //Oscillator Configuration Register
#define CCSR_OFFSET                          0xC      //Core Clock Status

#define CLKCFG_T                 0x1      // Turbo mode
#define CLKCFG_F                 0x2      // Frequnce change
#define CLKCFG_HT                0x4      // Frequnce change
#define CLKCFG_B                 0x8      // Fast-bus mode

//
//  BMAN:  inserted fwXsc1.inc here.  Not going to have this for bvd, since is really unnecessary
//

#define RCSR_ALL             0x1F        // bman: EAS 1.5 is a bit unclear// is bit 4 reserved or not? If so, then this value should be 0xF
#define Mode_SVC             0x13
#define Mode_USR             0x10
#define NoIntsMask           0x000000C0
#define IRQIntsMask          0x7F   // 0=enabled, 1=disabled
#define IrqFiqEnable         0xFFFFFF3F

//
// FLASH constants
//
#define K3_128Mb_DEVCODE           0x8806
#define J3_128Mb_DEVCODE           0x18

//
// Reset Controller Status Register bit defines
//
#define RCSR_HARD_RESET          (0x1)
#define RCSR_WDOG_RESET          (0x1 << 1)
#define RCSR_SLEEP_RESET         (0x1 << 2)
#define RCSR_GPIO_RESET          (0x1 << 3)
#define PSSR_VALID_MASK          0x3F
#define PSSR_OTGPH               (0x1 << 6)
#define PSSR_RDH                 (0x1 << 5)
#define PSSR_PH                  (0x1 << 4)

#define RCSR_GPR (1 << 3) /* GPIO Reset */
#define RCSR_SMR (1 << 2) /* Sleep Mode */
#define RCSR_WDR (1 << 1) /* Watchdog Reset */
#define RCSR_HWR (1 << 0) /* Hardware Reset */

//
// Clock Manager Defs
//
#define OSCC_OOK                 (0x1)
#define OSCC_OON                 (0x1 << 1)
#define OSCC_TOUT_EN             (0x1 << 2)
#define OSCC_PIO_EN              (0x1 << 3)
#define OSCC_CRI                 (0x1 << 4)
#define CKEN_DEFAULT             0x00400240        // MEMC, OST, FFUART clocked.  Rest OFF

//
//  Power Manager Defs
//
#define PCFR_OPDE                    (0x1)
#define PCFR_FP                      (0x1 << 1)
#define PCFR_FS                      (0x1 << 2)
#define PCFR_GPR_EN                  (0x1 << 4)
#define PCFR_SYSEN_EN                (0x1 << 5)
#define PCFR_PI2C_EN                 (0x1 << 6)
#define PCFR_DC_EN                   (0x1 << 7)
#define PCFR_FVC                     (0x1 << 10)
#define PCFR_L1_EN                   (0x1 << 11)
#define PCFR_GP_ROD                  (0x1 << 12)
#define PWER_WE0                     (0x1)
#define PWER_WE1                     (0x1 << 1)
#define PWER_WBB                     (0x1 << 25)
#define PWER_WEUSBC                  (0x1 << 26)
#define PWER_WEUSBH0                 (0x1 << 27)
#define PWER_WEUSBH1                 (0x1 << 28)
#define PWER_WEP1                    (0x1 << 30)
#define PWER_WERTC                   (0x1 << 31)
#define PMCR_BIDAE                   (0x1)
#define PMCR_BIDAS                   (0x1 << 1)
#define PMCR_VIDAE                   (0x1 << 2)
#define PMCR_VIDAS                   (0x1 << 3)
#define PMCR_IAS                     (0x1 << 4)
#define PMCR_INTRS                   (0x1 << 5)

// bman: get rid of these...
//
#define BIT0        (1 << 0)
#define BIT1        (1 << 1)
#define BIT2        (1 << 2)
#define BIT3        (1 << 3)
#define BIT4        (1 << 4)
#define BIT5        (1 << 5)
#define BIT6        (1 << 6)
#define BIT7        (1 << 7)
#define BIT8        (1 << 8)
#define BIT9        (1 << 9)
#define BIT10       (1 << 10)
#define BIT11       (1 << 11)
#define BIT12       (1 << 12)
#define BIT13       (1 << 13)
#define BIT14       (1 << 14)
#define BIT15       (1 << 15)
#define BIT16       (1 << 16)
#define BIT17       (1 << 17)
#define BIT18       (1 << 18)
#define BIT19       (1 << 19)
#define BIT20       (1 << 20)
#define BIT21       (1 << 21)
#define BIT22       (1 << 22)
#define BIT23       (1 << 23)
#define BIT24       (1 << 24)
#define BIT25       (1 << 25)
#define BIT26       (1 << 26)
#define BIT27       (1 << 27)
#define BIT28       (1 << 28)
#define BIT29       (1 << 29)
#define BIT30       (1 << 30)
#define BIT31       (1 << 31)

//
// Bit Positions for Primary Interrupt Sources
//
#define IP2_CIF         (0x1  << 1)    //Quick capture interface interrupt
#define IP2_XXX         (0x1  << 0)    //NA

#define IP_RTCALARM     (0x1u << 31)    //RTC equals Alarm register
#define IP_RTC_TIC      (0x1  << 30)    //One Hz clock TIC occurred
#define IP_OSMR3        (0x1  << 29)    //OS timer equals Match register 3
#define IP_OSMR2        (0x1  << 28)    //OS timer equals match register 2
#define IP_OSMR1        (0x1  << 27)    //OS timer equals Match register 1
#define IP_OSMR0        (0x1  << 26)    //OS timer equals Match register 0
#define IP_DMAC         (0x1  << 25)    //DMA Channel service request
#define IP_SSP          (0x1  << 24)    //SSP_1 service request
#define IP_MMC          (0x1  << 23)    //Flash card status/Error detection
#define IP_FFUART       (0x1  << 22)    //COMM
#define IP_BTUART       (0x1  << 21)    //Debug
#define IP_STUART       (0x1  << 20)    //IRDA
#define IP_ICP          (0x1  << 19)    //Transmit or receive error in infrared communications port
#define IP_I2C          (0x1  << 18)    //I2C service request
#define IP_LCD          (0x1  << 17)    //LCD controller service request
#define IP_SSP2         (0x1  << 16)    //SSP_2 service request
#define IP_USIM         (0x1  << 15)    //Smart card interface status/error
#define IP_AC97         (0x1  << 14)    //AC'97 interrupt
#define IP_I2S          (0x1  << 13)    //I2S interrupt
#define IP_PMU          (0x1  << 12)    //PMU(performance monitor) interrupt
#define IP_USB          (0x1  << 11)    //USB client interrupt
#define IP_GPIO80_2     (0x1  << 10)    //GPIO_<x> edge detect, except 0 and 1
#define IP_GPIO1        (0x1  << 9)     //GPIO_<1> detects an edge
#define IP_GPIO0        (0x1  << 8)     //GPIO_<0> detects an edge
#define IP_OSMRXX_4     (0x1  << 7)     //OS timer matches 4-11
#define IP_PWRI2C       (0x1  << 6)     //Power I2C interrupt
#define IP_MEMSTICK     (0x1  << 5)     //Memory stick interrupt
#define IP_KEYPAD       (0x1  << 4)     //keypad controller interrupt
#define IP_USBOHCI      (0x1  << 3)     //USB Host Interrupt 1(OHCI)
#define IP_USBNONOHCI   (0x1  << 2)     //USB Host interrupt 2
#define IP_BASEBAND     (0x1  << 1)
#define IP_SSP3         (0x1  << 0)     //SSP_3 service request

//
//  Bits used for Memory Controller Init
//
// register bit masks - mdcnfg
#define MDCNFG_DE0                   (BIT0)
#define MDCNFG_DE1                   (BIT1)
#define MDCNFG_DWID0                 (BIT2)
#define MDCNFG_DCAC0                 (BIT3+BIT4)
#define MDCNFG_DRAC0                 (BIT5+BIT6)
#define MDCNFG_DNB0                  (BIT7)
#define MDCNFG_DTC0                  (BIT8+BIT9)
#define MDCNFG_DADDR0                (BIT10)
#define MDCNFG_DLATCH0               (BIT11)
#define MDCNFG_RESERVED0             (BIT12+BIT13+BIT14+BIT15)
#define MDCNFG_DE2                   (BIT16)
#define MDCNFG_DE3                   (BIT17)
#define MDCNFG_DWID2                 (BIT18)
#define MDCNFG_DCAC2                 (BIT19+BIT20)
#define MDCNFG_DRAC2                 (BIT21+BIT22)
#define MDCNFG_DNB2                  (BIT23)
#define MDCNFG_DTC2                  (BIT24+BIT25)
#define MDCNFG_DADDR2                (BIT26)
#define MDCNFG_DLATCH2               (BIT27)
#define MDCNFG_RESERVED2             (BIT28+BIT29+BIT30+BIT31)

#define MDREFR_E0PIN                 0x00001000
#define MDREFR_K0RUN                 0x00002000
#define MDREFR_K1RUN                 0x00010000
#define MDREFR_K2RUN                 0x00040000
#define MDREFR_SLFRSH                0x00400000
#define MDREFR_E1PIN                 0x00008000
#define MDREFR_K1DB2                 0x00020000     // run SDCLK[1] @ .5(MClk)
#define MDREFR_K0DB2                 0x00004000
#define MDREFR_K0DB4                 0x20000000      // run SDCLK[0] @ .25(MemClk)
#define MDREFR_K0FREE                0x00800000
#define MDREFR_K1FREE                0x01000000
#define MDREFR_K2FREE                0x02000000
#define MDREFR_APD                   0x00100000
#define BANK_SHIFT                      20

/*
 * Core Clock
 */

#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */

//
// CCCR 'L' vals
//
#define CCCR_L02                 0x2
#define CCCR_L03                 0x3
#define CCCR_L04                 0x4
#define CCCR_L05                 0x5
#define CCCR_L06                 0x6
#define CCCR_L07                 0x7
#define CCCR_L08                 0x8
#define CCCR_L09                 0x9
#define CCCR_L10                 0xA
#define CCCR_L11                 0xB
#define CCCR_L12                 0xC
#define CCCR_L13                 0xD
#define CCCR_L14                 0xE
#define CCCR_L15                 0xF
#define CCCR_L16                 0x10
#define CCCR_L17                 0x11
#define CCCR_L18                 0x12
#define CCCR_L19                 0x13
#define CCCR_L20                 0x14
#define CCCR_L21                 0x15
#define CCCR_L22                 0x16
#define CCCR_L23                 0x17
#define CCCR_L24                 0x18
#define CCCR_L25                 0x19
#define CCCR_L26                 0x1A
#define CCCR_L27                 0x1B
#define CCCR_L28                 0x1C
#define CCCR_L29                 0x1D
#define CCCR_L30                 0x1E
#define CCCR_L31                 0x1F

//
// CCCR 'N' vals
//
#define CCCR_N1p0                 (0x2 << 7)
#define CCCR_N1p5                 (0x3 << 7)
#define CCCR_N2p0                 (0x4 << 7)
#define CCCR_N2p5                 (0x5 << 7)
#define CCCR_N3p0                 (0x6 << 7)

//
// Core Clock Configuration Register (CCCR) Bits
//
#define CCCR_L             (0x1fu << 0)
#define CCCR_2N            (0x0fu << 7)
#define CCCR_A             (0x1u << 25)
#define CCCR_PLL_EARLY_EN  (0x1u << 26)
#define CCCR_LCD26         (0x1u << 27)
#define CCCR_PPDIS         (0x1u << 30)
#define CCCR_CPDIS         (0x1u << 31)

#define CCCR_2N_MASK 0x0380  /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
#define CCCR_M_MASK  0x0060  /* Memory Frequency to Run Mode Frequency Multiplier */
#define CCCR_L_MASK  0x001f  /* Crystal Frequency to Memory Frequency Multiplier */
//
//  OSC/Clock Defs
//
#define PLATFORM_MEMORY            CCCR_L27
#define CORE_CLK_100MHZ            (PLATFORM_MEMORY | CCCR_M1 | CCCR_N20)
#define CORE_CLK_200MHZ            (PLATFORM_MEMORY | CCCR_M2 | CCCR_N20)

#define OSSR_M3     (1 << 3)    /* Match status channel 3 */
#define OSSR_M2     (1 << 2)    /* Match status channel 2 */
#define OSSR_M1     (1 << 1)    /* Match status channel 1 */
#define OSSR_M0     (1 << 0)    /* Match status channel 0 */

#define OWER_WME    (1 << 0)    /* Watchdog Match Enable */

#define OIER_E3     (1 << 3)    /* Interrupt enable channel 3 */
#define OIER_E2     (1 << 2)    /* Interrupt enable channel 2 */
#define OIER_E1     (1 << 1)    /* Interrupt enable channel 1 */
#define OIER_E0     (1 << 0)    /* Interrupt enable channel 0 */

//   Bits used for CP 15
//
#define CONTROL_MMU                0x00000001

// Bits for CKEN
//
#define CKEN22_MEMC    (1 << 22)   /* Memory controler */
#define CKEN16_LCD     (1 << 16)   /* LCD Unit Clock Enable */
#define CKEN14_I2C     (1 << 14)   /* I2C Unit Clock Enable */
#define CKEN13_FICP    (1 << 13)   /* FICP Unit Clock Enable */
#define CKEN12_MMC     (1 << 12)   /* MMC Unit Clock Enable */
#define CKEN11_USB     (1 << 11)   /* USB Unit Clock Enable */
#define CKEN9_OSTIMER  (1 << 9)    /* OS Timer Unit Clock Enable */
#define CKEN8_I2S      (1 << 8)    /* I2S Unit Clock Enable */
#define CKEN7_BTUART   (1 << 7)    /* BTUART Unit Clock Enable */
#define CKEN6_FFUART   (1 << 6)    /* FFUART Unit Clock Enable */
#define CKEN5_STUART   (1 << 5)    /* STUART Unit Clock Enable */
#define CKEN4_HWUART   (1 << 4)    /* HWUART Unit Clock Enable */
#define CKEN3_SSP      (1 << 3)    /* SSP Unit Clock Enable */
#define CKEN2_AC97     (1 << 2)    /* AC97 Unit Clock Enable */
#define CKEN1_PWM1     (1 << 1)    /* PWM1 Clock Enable */
#define CKEN0_PWM0     (1 << 0)    /* PWM0 Clock Enable */

// Shifts for MSC0/1/2
//
#define MSC_RBUFFx  15  /* 15,    Return data BUFFer vs. streaming behavior */
#define MSC_RRRx    14  /* 14:12, ROM/SRAM Recovery time */
#define MSC_RDNx    11  /* 11:8,  ROM Delay Next access */
#define MSC_RDFx    7   /* 7:4,   The ROM Delay First access field is encoded */
#define MSC_RBWx    3   /* 3,     RBWx ROM bus width */
#define MSC_RTx     2   /* 2:0,   Rom Type */

#define MSC_RBW_16  0
#define MSC_RBW_32  1

#define MSC_RT_ROM  0
#define MSC_RT_SRAM 1
#define MSC_RT_BURST4   2
#define MSC_RT_BURST8   3
#define MSC_RT_VLIO 4

#define IER_DMAE    (1 << 7)    /* DMA Requests Enable */
#define IER_UUE     (1 << 6)    /* UART Unit Enable */
#define IER_NRZE    (1 << 5)    /* NRZ coding Enable */
#define IER_RTIOE   (1 << 4)    /* Receiver Time Out Interrupt Enable */
#define IER_MIE     (1 << 3)    /* Modem Interrupt Enable */
#define IER_RLSE    (1 << 2)    /* Receiver Line Status Interrupt Enable */
#define IER_TIE     (1 << 1)    /* Transmit Data request Interrupt Enable */
#define IER_RAVIE   (1 << 0)    /* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1 (1 << 7)    /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6)    /* FIFO Mode Enable Status */
#define IIR_TOD     (1 << 3)    /* Time Out Detected */
#define IIR_IID2    (1 << 2)    /* Interrupt Source Encoded */
#define IIR_IID1    (1 << 1)    /* Interrupt Source Encoded */
#define IIR_IP      (1 << 0)    /* Interrupt Pending (active low) */

#define FCR_ITL2    (1 << 7)    /* Interrupt Trigger Level */
#define FCR_ITL1    (1 << 6)    /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2)    /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1)    /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0)    /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1   (0)
#define FCR_ITL_8   (FCR_ITL1)
#define FCR_ITL_16  (FCR_ITL2)
#define FCR_ITL_32  (FCR_ITL2|FCR_ITL1)

#define LCR_DLAB    (1 << 7)    /* Divisor Latch Access Bit */
#define LCR_SB      (1 << 6)    /* Set Break */
#define LCR_STKYP   (1 << 5)    /* Sticky Parity */
#define LCR_EPS     (1 << 4)    /* Even Parity Select */
#define LCR_PEN     (1 << 3)    /* Parity Enable */
#define LCR_STB     (1 << 2)    /* Stop Bit */
#define LCR_WLS1    (1 << 1)    /* Word Length Select */
#define LCR_WLS0    (1 << 0)    /* Word Length Select */

#define LSR_FIFOE   (1 << 7)    /* FIFO Error Status */
#define LSR_TEMT    (1 << 6)    /* Transmitter Empty */
#define LSR_TDRQ    (1 << 5)    /* Transmit Data Request */
#define LSR_BI      (1 << 4)    /* Break Interrupt */
#define LSR_FE      (1 << 3)    /* Framing Error */
#define LSR_PE      (1 << 2)    /* Parity Error */
#define LSR_OE      (1 << 1)    /* Overrun Error */
#define LSR_DR      (1 << 0)    /* Data Ready */

#define MCR_AFE     (1 << 5)    /* Autoflow Control Enable */
#define MCR_LOOP    (1 << 4)    /* Loopback mode */
#define MCR_OUT2    (1 << 3)    /* force MSR_DCD in loopback mode */
#define MCR_OUT1    (1 << 2)    /* force MSR_RI in loopback mode */
#define MCR_RTS     (1 << 1)    /* Request to Send */
#define MCR_DTR     (1 << 0)    /* Data Terminal Ready */

#define MSR_DCD     (1 << 7)    /* Data Carrier Detect */
#define MSR_RI      (1 << 6)    /* Ring Indicator */
#define MSR_DSR     (1 << 5)    /* Data Set Ready */
#define MSR_CTS     (1 << 4)    /* Clear To Send */
#define MSR_DDCD    (1 << 3)    /* Delta Data Carrier Detect */
#define MSR_TERI    (1 << 2)    /* Trailing Edge Ring Indicator */
#define MSR_DDSR    (1 << 1)    /* Delta Data Set Ready */
#define MSR_DCTS    (1 << 0)    /* Delta Clear To Send */

/* Interrupt Controller */

#define ICIP        __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
#define ICMR        __REG(0x40D00004)  /* Interrupt Controller Mask Register */
#define ICLR        __REG(0x40D00008)  /* Interrupt Controller Level Register */
#define ICFP        __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
#define ICPR        __REG(0x40D00010)  /* Interrupt Controller Pending Register */
#define ICCR        __REG(0x40D00014)  /* Interrupt Controller Control Register */

/* GPIO registers */

#define GPLR0       __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1       __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2       __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<95:64> */

#define GPDR0       __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1       __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2       __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<95:64> */

#define GPSR0       __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1       __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2       __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<95:64> */

#define GPCR0       __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1       __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2       __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <95:64> */

#define GRER0       __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1       __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2       __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<95:64> */

#define GFER0       __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1       __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2       __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<95:64> */

#define GEDR0       __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1       __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2       __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<95:64> */

#define GAFR0_L     __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U     __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L     __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U     __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L     __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U     __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO <95:80> */
#define GAFR3_L     __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
#define GAFR3_U     __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO <120:112> */

#define GPLR3       __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<120:96> */
#define GPDR3       __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<120:96> */
#define GPSR3       __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<120:96> */
#define GPCR3       __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO <120:96> */
#define GRER3       __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<120:96> */
#define GFER3       __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<120:96> */
#define GEDR3       __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<120:96> */

/* OS Timer Registers */

#define OSMR0       __REG(0x40A00000)  /* */
#define OSMR1       __REG(0x40A00004)  /* */
#define OSMR2       __REG(0x40A00008)  /* */
#define OSMR3       __REG(0x40A0000C)  /* */
#define OSCR        __REG(0x40A00010)  /* OS Timer Counter Register */
#define OSSR        __REG(0x40A00014)  /* OS Timer Status Register */
#define OWER        __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
#define OIER        __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */

#define OSCR0       __REG(0x40A00010)  /* OS Timer Counter Register */

/* Power Manager Registers */

#define PMCR        __REG(0x40F00000)            /* Power Manager Control Register */
#define PSSR        __REG(0x40F00004)            /* Power Manager Sleep Status Register */
#define PSPR        __REG(0x40F00008)            /* Power Manager Scratch Pad Register */
#define PWER        __REG(0x40F0000C)            /* Power Manager Wake-up Enable Register */
#define PRER        __REG(0x40F00010)            /* Power Manager GPIO Rising-Edge Detect Enable Register */
#define PFER        __REG(0x40F00014)            /* Power Manager GPIO Falling-Edge Detect Enable Register */
#define PEDR        __REG(0x40F00018)            /* Power Manager GPIO Edge Detect Status Register */
#define PCFR        __REG(0x40F0001C)            /* Power Manager General Configuration Register */
#define PGSR0       __REG(0x40F00020)            /* Power Manager GPIO Sleep State Register for GP[31-0] */
#define PGSR1       __REG(0x40F00024)            /* Power Manager GPIO Sleep State Register for GP[63-32] */
#define PGSR2       __REG(0x40F00028)            /* Power Manager GPIO Sleep State Register for GP[95-64] */
#define PGSR3       __REG(0x40F0002C)            /* Power Manager GPIO Sleep State Register for GP[120-96] */
#define RCSR        __REG(0x40F00030)            /* Reset Controller Status Register */
#define PSLR        __REG( 0x40F00034 )          //  Power Manager Sleep Mode Configuration register
#define PSTR        __REG( 0x40F00038 )          //  Power Manager Standby Mode Configuration register
#define PSNR        __REG( 0x40F0003C )          //  Power Manager Sense Mode Configuration register
#define PVCR        __REG( 0x40F00040 )          //  Power Manager Voltage Change Control register
#define PKWR        __REG( 0x40F00050 )          //  Power Manager Wake-up Enable for Keyboard
#define PKSR        __REG( 0x40F00054 )          //  Power Manager Keyboard wakeup status Register

/* Memory Controller Registers*/

#define MDCNFG      __REG(0x48000000)  /* SDRAM Configuration Register 0 */
#define MDREFR      __REG(0x48000004)  /* SDRAM Refresh Control Register */
#define MSC0        __REG(0x48000008)  /* Static Memory Control Register 0 */
#define MSC1        __REG(0x4800000C)  /* Static Memory Control Register 1 */
#define MSC2        __REG(0x48000010)  /* Static Memory Control Register 2 */
#define MECR        __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
#define SXLCR       __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
#define SXCNFG      __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
#define SXMRS       __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
#define MCMEM0      __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
#define MCMEM1      __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
#define MCATT0      __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
#define MCATT1      __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
#define MCIO0       __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
#define MCIO1       __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
#define MDMRS       __REG(0x48000040)  /* MRS value to be written to SDRAM */
#define BOOT_DEF    __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */

/* Bluetooth UART (BTUART) */
#define BTUART      BTRBR
#define BTRBR       __REG(0x40200000)  /* Receive Buffer Register (read only) */
#define BTTHR       __REG(0x40200000)  /* Transmit Holding Register (write only) */
#define BTIER       __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
#define BTIIR       __REG(0x40200008)  /* Interrupt ID Register (read only) */
#define BTFCR       __REG(0x40200008)  /* FIFO Control Register (write only) */
#define BTLCR       __REG(0x4020000C)  /* Line Control Register (read/write) */
#define BTMCR       __REG(0x40200010)  /* Modem Control Register (read/write) */
#define BTLSR       __REG(0x40200014)  /* Line Status Register (read only) */
#define BTMSR       __REG(0x40200018)  /* Modem Status Register (read only) */
#define BTSPR       __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
#define BTISR       __REG(0x40200020)  /* Infrared Selection Register (read/write) */
#define BTDLL       __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define BTDLH       __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

/* Standard UART (STUART) */
#define STUART      STRBR
#define STRBR       __REG(0x40700000)  /* Receive Buffer Register (read only) */
#define STTHR       __REG(0x40700000)  /* Transmit Holding Register (write only) */
#define STIER       __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
#define STIIR       __REG(0x40700008)  /* Interrupt ID Register (read only) */
#define STFCR       __REG(0x40700008)  /* FIFO Control Register (write only) */
#define STLCR       __REG(0x4070000C)  /* Line Control Register (read/write) */
#define STMCR       __REG(0x40700010)  /* Modem Control Register (read/write) */
#define STLSR       __REG(0x40700014)  /* Line Status Register (read only) */
#define STMSR       __REG(0x40700018)  /* Reserved */
#define STSPR       __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
#define STISR       __REG(0x40700020)  /* Infrared Selection Register (read/write) */
#define STDLL       __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH       __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */

/* Hardware UART (HWUART)  */
#define HWUART      HWRBR
#define HWRBR       __REG(0x41600000)  /* Receive Buffer Register (read only) */
#define HWTHR       __REG(0x41600000)  /* Transmit Holding Register (write only) */
#define HWIER       __REG(0x41600004)  /* Interrupt Enable Register (read/write) */
#define HWIIR       __REG(0x41600008)  /* Interrupt ID Register (read only) */
#define HWFCR       __REG(0x41600008)  /* FIFO Control Register (write only) */
#define HWLCR       __REG(0x4160000C)  /* Line Control Register (read/write) */
#define HWMCR       __REG(0x41600010)  /* Modem Control Register (read/write) */
#define HWLSR       __REG(0x41600014)  /* Line Status Register (read only) */
#define HWMSR       __REG(0x41600018)  /* Modem Status register */
#define HWSPR       __REG(0x4160001C)  /* Scratch Pad Register (read/write) */
#define HWISR       __REG(0x41600020)  /* Infrared Selection Register (read/write) */
#define HWFOR       __REG(0x41600024)  /* FIFO Occupancy register (read-only) */
#define HWABR       __REG(0x41600028)  /* Autobaud Control register (read/write) */
#define HWACR       __REG(0x4160002C)  /* Autobaund Count register */
#define HWDLL       __REG(0x41600000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define HWDLH       __REG(0x41600004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* MMC controller*/
#define MMCSTRPCL   __REG(0x41100000)
#define MMCSTAT     __REG(0x41100004)
#define MMCCLKRT    __REG(0x41100008)
#define MMCCMDAT    __REG(0x41100010)
#define MMCRESTO    __REG(0x41100014)
#define MMCBLKLEN   __REG(0x4110001c)
#define MMCCMD      __REG(0x41100030)
#define MMCARGH     __REG(0x41100034)
#define MMCARGL     __REG(0x41100038)
#define MMCRES      __REG(0x4110003c)
#define MMCIMASK    __REG(0x41100028)
#define MMCIREG     __REG(0x4110002c)
#define MMCRXFIFO   0x41100040
#define MMCTXFIFO   0x41100044
#define MMCNUMBLK   __REG(0x41100020)

/*SSP*/

#define BV_SSCR0_1    __REG(0x41000000)
#define BV_SSCR1_1    __REG(0x41000004 )          //    SSP1 Control register 1
#define BV_SSSR_1     __REG(0x41000008 )          //    SSP1 Status register
#define BV_SSITR_1    __REG(0x4100000C )          //    SSP1 Interrupt Test register
#define BV_SSDR_1     __REG(0X41000010 )          //    SSP1 Data Write Register/SSP1 Data Read register
#define BV_SSTO_1     __REG(0x41000028 )          //    SSP1 Time Out register
#define BV_SSPSP_1    __REG(0x4100002c)           //    SSP1 Programmable Serial Protocol

#define SSCR0_SCR           (1<<8)
#define SSCR0_SSE                   (1<<7)
#define SSCR0_FRF                   (1<<4)
#define SSCR0_DSS                   (1<<0)

#define SSCR1_RX_THRESSHOLD         (1<<10)
#define SSCR1_TX_THRESSHOLD         (1<<6)
#define SSCR1_SPH                   (1<<4)
#define SSCR1_SPO                   (1<<3)

#define SSSR_RFL                    (1<<12)
#define SSSR_TFL                    (1<<8)
#define SSSR_BSY                    (1<<4)
#define SSSR_RNE                    (1<<3)

#define SSPSP_DUMMY_STOP            (1<<23)

#define SSPSP_SCMODE                (1<<0)

#define SSP_FIFO_DEEP               16      // both RX & TX

// I2C control registers

#define BV_IBMR         __REG(0x40301680)          //    Bus Monitor register
#define BV_IDBR         __REG(0x40301688)          //    Data Buffer register
#define BV_ICR          __REG(0x40301690)         //    Control register
#define BV_ISR          __REG(0x40301698 )          //    Status register
#define BV_ISAR         __REG(0x403016A0 )         //    Slave Address register
 // I2C

#define I2C_ICR_UR                  (1<<14)             // Unit Reset
#define I2C_ICR_ALDIE               (1<<12)             // Arbitration-Loss-Detected interrupt enable
#define I2C_ICR_GCD                 (1<<7)              // General Call Disable
#define I2C_ICR_IUE                 (1<<6)              // I2C Unit Enable
#define I2C_ICR_SCLEA               (1<<5)              // SCL Enable for master-mode operation
#define I2C_ICR_MA                  (1<<4)              // Master Abort without transmitting another data byte
#define I2C_ICR_TB                  (1<<3)              // Transfer Byte
#define I2C_ICR_ACKNAK              (1<<2)              // '0' for ACK & '1' for NAK
#define I2C_ICR_STOP                (1<<1)              // A STOP condition after next data byte
#define I2C_ICR_START               (1<<0)              // Initiate a START condition

#define I2C_ISR_BED                 (1<<10)             // Bus Error Detected
#define I2C_ISR_IRF                 (1<<7)              // IDBR Receive Full
#define I2C_ISR_ITE                 (1<<6)              // IDBR Transmit Empty
#define I2C_ISR_ALD                 (1<<5)              // Arbitration Loss Detected
#define I2C_ISR_IBB                 (1<<3)              // I2C Bus Busy
#define I2C_ISR_UB                  (1<<2)              // Unit Busy

// I2S control registers

#define BV_SACR0        __REG(0x40400000)          //    Global Control register
#define BV_SACR1        __REG(0x40400004)          //    Serial Audio I2S/MSB-Justified Control register
#define BV_SASR0        __REG(0x4040000C)          //    Serial Audio I2S/MSB-Justified Interface and FIFO Status register
#define BV_SAIMR        __REG(0x40400014)          //    Serial Audio Interrupt Mask register
#define BV_SAICR        __REG(0x40400018)          //    Serial Audio Interrupt Clear register
#define BV_SADIV        __REG(0x40400060)          //    Audio clock divider register. See section 22.3 Serial Audio Clocks and Sampling frequencies on page 22-7.
#define BV_SADR         __REG(0x40400080)          //    Serial Audio Data Register (TX and RX FIFO access register).

// I2S

#define SACR0_RFTH                  (1<<12)
#define SACR0_TFTH                  (1<<8)
#define SACR0_RST                   (1<<3)
#define SACR0_BCKD                  (1<<2)
#define SACR0_ENB                   (1<<0)

#define SACR1_DRPL                  (1<<4)
#define SACR1_DREC                  (1<<3)

#define SASR0_RFL                   (1<<12)
#define SASR0_TFL                   (1<<8)
#define SASR0_OFF                   (1<<7)
#define SASR0_BSY                   (1<<2)
#define SASR0_RNE                   (1<<1)
#define SASR0_TNF                   (1<<0)

// I2S

#define I2S_SAM_FEQ_48              0x0C
#define I2S_SAM_FEQ_44              0x0D
#define I2S_SAM_FEQ_22              0x1A
#define I2S_SAM_FEQ_16              0x24
#define I2S_SAM_FEQ_11              0x34
#define I2S_SAM_FEQ_8               0x48

#define I2S_FIFO_DEEP               16      // both RX & TX

/*IRQ*/

#define IER_DMAE    (1 << 7)    /* DMA Requests Enable */
#define IER_UUE     (1 << 6)    /* UART Unit Enable */
#define IER_NRZE    (1 << 5)    /* NRZ coding Enable */
#define IER_RTIOE   (1 << 4)    /* Receiver Time Out Interrupt Enable */
#define IER_MIE     (1 << 3)    /* Modem Interrupt Enable */
#define IER_RLSE    (1 << 2)    /* Receiver Line Status Interrupt Enable */
#define IER_TIE     (1 << 1)    /* Transmit Data request Interrupt Enable */
#define IER_RAVIE   (1 << 0)    /* Receiver Data Available Interrupt Enable */

#define IIR_FIFOES1 (1 << 7)    /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6)    /* FIFO Mode Enable Status */
#define IIR_TOD     (1 << 3)    /* Time Out Detected */
#define IIR_IID2    (1 << 2)    /* Interrupt Source Encoded */
#define IIR_IID1    (1 << 1)    /* Interrupt Source Encoded */
#define IIR_IP      (1 << 0)    /* Interrupt Pending (active low) */

/* Bulverde USB register's definition */
#define UP2OCR  __REG(0x40600020)

#define UDCCR        __REG(0x40600000)
#define UDCICR0      __REG(0x40600004)
#define UDCICR1      __REG(0x40600008)
#define UDCISR0      __REG(0x4060000c)
#define UDCISR1      __REG(0x40600010)
#define UDCFNR       __REG(0x40600014)

#define UDCCSR(x)    __REG(0x40600100|(x<<2))
#define UDCCSRA      __REG(0x40600104)
#define UDCCSRB      __REG(0x40600108)
/* Omit endpoint C~X */

#define UDCBCR(x)    __REG(0x40600200|(x<<2))
#define UDCBCRA      __REG(0x40600204)
#define UDCBCRB      __REG(0x40600208)
/* Omit endpoint C~X */

#define UDCDR(x)     __REG(0x40600300|(x<<2))
#define UDCDRA       __REG(0x40600304)
#define UDCDRB       __REG(0x40600308)
/* Omit endpiont C~X */

#define UDCCRA       __REG(0x40600404)
#define UDCCRB       __REG(0x40600408)
/* Omit endpoint C~X */

/* USB register bit definitions */

#define UDCCR_UDE    (1 << 0)
#define UDCCR_UDA    (1 << 1)
#define UDCCR_UDR    (1 << 2)
#define UDCCR_EMCE   (1 << 3)
#define UDCCR_SMAC   (1 << 4)
#define UDCCR_AAISN  (1 << 5)
#define UDCCR_AIN    (1 << 8)
#define UDCCR_ACN    (1 << 11)
#define UDCCR_DWRE   (1 << 16)

#define UDCICR0_IE0  (1 << 0)
#define UDCICR0_IEA  (1 << 2)
#define UDCICR0_IEB  (1 << 4)
/* Omit endpoint C~X */

#define UDCICR1_IERS (1 << 27)
#define UDCICR1_IESU (1 << 28)
#define UDCICR1_IERU (1 << 29)
#define UDCICR1_IESOF (1 << 30)
#define UDCICR1_IECC (1 << 31)

#define UDCISR0_IR0  (1 << 0)
#define UDCISR0_IRA  (1 << 2)
#define UDCISR0_IRB  (1 << 4)
/* Omit endpiont C~X */

#define UDCISR1_IRRS  (1 << 27)
#define UDCISR1_IRSU  (1 << 28)
#define UDCISR1_IRRU  (1 << 29)
#define UDCISR1_IRSOF (1 << 30)
#define UDCISR1_IRCC  (1 << 31)

#define UDCCSR0_OPC  (1 << 0)
#define UDCCSR0_IPR  (1 << 1)
#define UDCCSR0_FTF  (1 << 2)
#define UDCCSR0_DME  (1 << 3)
#define UDCCSR0_SST  (1 << 4)
#define UDCCSR0_FST  (1 << 5)
#define UDCCSR0_RNE  (1 << 6)
#define UDCCSR0_SA   (1 << 7)

#define UDCCSR_FS    (1 << 0)
#define UDCCSR_PC    (1 << 1)
#define UDCCSR_TRN   (1 << 2)
#define UDCCSR_DME   (1 << 3)
#define UDCCSR_SST   (1 << 4)
#define UDCCSR_FST   (1 << 5)
#define UDCCSR_BNE   (1 << 6)
#define UDCCSR_BNF   (1 << 6)
#define UDCCSR_SP    (1 << 7)
#define UDCCSR_FEF   (1 << 8)
#define UDCCSR_DPE   (1 << 9)

#define UDCCRB_EE    (1 << 0)
#define UDCCRB_DE    (1 << 1)
#define UDCCRB_MPS   (1 << 2)
#define UDCCRB_ED    (1 << 12)
#define UDCCRB_ET    (1 << 13)
#define UDCCRB_EN    (1 << 15)
#define UDCCRB_AISN  (1 << 19)
#define UDCCRB_IN    (1 << 22)
#define UDCCRB_CN    (1 << 25)

#define UDCECR(x)           __REG(0x40600400|(x << 2))  /* UDC Endpoints x Control Register*/
#define UDCECR_CN_MASK      (0x3 << 25) /* Configuration Number */
#define UDCECR_CN_SHIFT     25
#define UDCECR_IN_MASK      (0x7 << 22) /* Intertface Number */
#define UDCECR_IN_SHIFT     22
#define UDCECR_AISN_MASK    (0x7 << 19) /* Alternate Interface Number */
#define UDCECR_AISN_SHIFT   19
#define UDCECR_EN_MASK      (0xf << 15) /* Endpoint Number */
#define UDCECR_EN_SHIFT     15
#define UDCECR_ET_MASK      (0x3 << 13) /* Endpoint Number */
#define UDCECR_ET_SHIFT     13 /* Endpoint Type */
#define UDCECR_ED           (1 << 12) /* Endpoint Direction 1 = IN */
#define UDCECR_ED_SHIFT     12
#define UDCECR_MPS_MASK     (0x3ff << 2) /* Max packet size */
#define UDCECR_MPS_SHIFT    2
#define UDCECR_DE           (1 << 1) /* Double buffer enable */
#define UDCECR_DE_SHIFT     1
#define UDCECR_EE           (1 << 0) /* Endpoint Enable */

#define UDCECR_ED_IN        1
#define UDCECR_ED_OUT       0
#define UDCECR_DE_DBLBUF    1
#define UDCECR_DE_SGLBUF    0
#define UDCECR_ET_INT       0x3 /* Endpoint Type - Interrupt */
#define UDCECR_ET_BULK      0x2 /* Endpoint Type - Bulk */
#define UDCECR_ET_ISO       0x1 /* Endpoint Type - isochronous */

#define UDCECR_SETUP(x, cn, in, aisn, en, et, ed, mps, de)  \
            UDCECR(x) = (((cn) << UDCECR_CN_SHIFT) | ((in) << UDCECR_IN_SHIFT) | \
                ((aisn) << UDCECR_AISN_SHIFT) | ((en) << UDCECR_EN_SHIFT) | \
                ((et) << UDCECR_ET_SHIFT) | ((ed) << UDCECR_ED_SHIFT) | \
                ((mps) << UDCECR_MPS_SHIFT) | \
                ((de) << UDCECR_DE_SHIFT) | UDCECR_EE )

/**DMA**/
#define DCSR_BASE       0x40000000
#define DDADR_BASE      0x40000200
#define DSADR_BASE      0x40000204
#define DTADR_BASE      0x40000208
#define DCMD_BASE       0x4000020c

#define DCSR(i)     __REG(DCSR_BASE |(i<<2))
#define DDADR(i)    __REG(DDADR_BASE|(i*0x10))
#define DSADR(i)    __REG(DSADR_BASE|(i*0x10))
#define DTADR(i)    __REG(DTADR_BASE|(i*0x10))
#define DCMD(i)     __REG(DCMD_BASE|(i*0x10))
#define DRCMRRRMMC  __REG(0x40000154)
#define DRCMRTRMMC  __REG(0x40000158)
#define DRCMRCI0    __REG(0x40001110)          //DRCMR68
#define DRCMRCI1    __REG(0x40001114)          //DRCMR69
#define DRCMRCI2    __REG(0x40001118)          //DRCMR70
#define DINT        __REG(0x400000f0)

/*PWM*/
#define PWMCR0       __REG(0x40b00000)
#define PWMDCR0      __REG(0x40b00004)
#define PWMPCR0      __REG(0x40b00008)
#define PWMCR_SD    (1<<6)
#define PWMDCR_FD   (1<<10)

/*camera*/
#define CICR0   __REG(0x50000000)
#define CICR1   __REG(0x50000004)
#define CICR2   __REG(0x50000008)
#define CICR3   __REG(0x5000000C)
#define CICR4   __REG(0x50000010)
#define CISR    __REG(0x50000014)
#define CIFR    __REG(0x50000018)
#define CITOR   __REG(0x5000001C)
#define CIBR0   __REG(0x50000028)
#define CIBR1   __REG(0x50000030)
#define CIBR2   __REG(0x50000038)

/*keypad*/
#define KPC   __REG( 0x41500000 )          //  Keypad Interface Control register

#endif
